STM32 GPIO

All GPIO configurations ares controlled by GPIOx_CRL and GPIOx_CRH

GPIO Output

  • push-pull
    • CNF[1:0] = 00
    • MODE[1:0]
      • 00 = reserved
      • 01 = Max. output speed 10 MHz
      • 10 = Max. output speed 2 MHz
      • 11 = Max. output speed 50 MHz
  • open-drain
    • CNF[1:0] = 01
    • MODE[1:0]
      • 00 = reserved
      • 01 = Max. output speed 10 MHz
      • 10 = Max. output speed 2 MHz
      • 11 = Max. output speed 50 MHz

GPIO Input

  • Analog
    • CNF[1:0] = 00
    • MODE[1:0] = 00
  • Input floating
    • CNF[1:0] = 01
    • MODE[1:0] = 00
  • Input pull-up
    • CNF[1:0] = 10
    • MODE[1:0] = 00
    • GPIOx_ODR = 1
  • Input pull-down
    • CNF[1:0] = 10
    • MODE[1:0] = 00
    • GPIOx_ODR = 0

GPIOx_ODR

From bits 0 to 15, each bit corresponds each port going from port 0 to port 15. Upper half word (bits from 16 to 31) are reserved and must be zeroed.

GPIOx_BSRR

The register has two halves: from bit 0 to bit 15 and from bit 16 to bit 31. First half [15:0] is bit set, meaning for each 1 will output high into the corresponding port. Second half [31:16] is bit reset, meaning each 1 will output low into the corresponding port. In second half, bit 16 means port 0, bit 17 means port 1, and so one until bit 31 meaning port 15.

GPIOx_CRL

Configure from port n (0..7) registers CNFn and MODEn. Each port has 4 bits, which means port 0 has bits 3:0, port 1 bits 7:4 and so one until port 7 bits 31:28. This four bits means: CONF[1:0] MODE[1:0].

Example: default value 0x4444.4444 means CNF 01, MODE 00 to all ports from port 0 to port 7

GPIOx_CRH

Almost the same as CPIOx_CRL but for port 8 to port 15.

Configure from port n (8..15) registers CNFn and MODEn. Each port has 4 bits, which means port 0 has bits 3:0, port 1 bits 7:4 and so one until port 7 bits 31:28. This four bits means: CONF[1:0] MODE[1:0].

GPIOx_IDR

  • Bits 31:16 = reserved
  • Bits 15:0 = Ports IDR15..IDR0